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isplsi 8840v 3.3v in-system programmable superbig high density pld 8840v_03 1 copyright ?2000 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com features superbig high density in-system programmable logic 3.3v power supply 45,000 pld gates/840 macrocells 192-312 i/o pins supporting 3.3v/2.5v i/o 1152 registers high-speed global and big fast megablock (bfm) interconnect wide 20-macrocell generic logic block (glb) for high performance wide input gating (44 inputs per glb) for fast counters, state machines, address decoders, etc. pcb-efficient ball grid array (bga) package options high-performance e 2 cmos technology f max = 125 mhz maximum operating frequency t pd = 8.5 ns propagation delay electrically erasable and reprogrammable non-volatile programmable speed/power logic path optimization in-system programmable ?increased manufacturing yields, reduced time-to- market and improved product quality ?reprogram soldered devices for faster debugging 100% ieee 1149.1 boundary scan testable and 3.3v in-system programmable architecture features enhanced pin-locking architecture, symmetrical generic logic blocks connected by hierarchical big fast megablock and global routing planes product term sharing array supports up to 28 product terms per macrocell output macrocells support concurrent combinatorial and registered functions embedded tristate bus can be used as an internal tristate bus or as an extension of an external tristate bus macrocell and i/o registers feature multiple control options, including set, reset and clock enable i/o pins support programmable bus hold, pull-up, open-drain and slew rate options separate vccio power supply to support 3.3v or 2.5v input/output logic levels i/o cell register programmable as input register for fast setup time or output register for fast clock to output time ispdesignexpert ?logic compiler and com- plete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer pc and unix platforms functional block diagram isplsi 8000v family description the isplsi 8000v family of register-intensive, 3.3v superbig in-system programmable logic devices is based on big fast megablocks of 120 registered macro- cells and a global routing plane (grp) structure interconnecting the big fast megablocks. each big fast megablock contains 120 registered macrocells arranged in six groups of 20, a group of 20 being referred to as a generic logic block, or glb. within the big fast megablock, a big fast megablock routing pool (brp) interconnects the six glbs to each other and to 24 big global routing plane 12 i/o 12 i/o big fast megablock 0 12 i/o 12 i/o big fast megablock 1 12 i/o 12 i/o big fast megablock 3 12 i/o 12 i/o big fast megablock 4 12 i/o 12 i/o big fast megablock 6 12 i/o 12 i/o big fast megablock 5 12 i/o 12 i/o big fast megablock 2 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o 12 i/o boundary scan 8840v block july 2000
specifications isplsi 8840v 2 figure 1. isplsi 8840v functional block diagram (perspective) global routing plane (grp) with tristate bus lines big fast megablock routing pool (brp) big fast megablock routing pool (brp) big fast megablock routing pool (brp) big fast megablock routing pool (brp) functional block diagram
specifications isplsi 8840v 3 fast megablock i/o cells with optional i/o registers. the global routing plane which interconnects the big fast megablocks has additional global i/os with optional i/o registers. the 192-i/o version contains 72 big fast megablock i/os and 120 global i/os, while the 312-i/o version contains 168 big fast megablock i/os and 144 global i/os. outputs from the glbs in a big fast megablock can drive both the big fast megablock routing pool within the big fast megablock and the global routing plane between the big fast megablocks. switching resources are pro- vided to allow signals in the global routing plane to drive any or all the big fast megablocks in the device. this mechanism allows fast, efficient connections, both within the big fast megablocks and between them. each glb contains 20 macrocells and a fully populated, programmable and-array with 82 logic product terms. the glb has 44 inputs from the big fast megablock routing pool which are available in both true and comple- ment form for every product term. up to 20 of these inputs can be switched to provide local feedback into the glb for logic functions that require it. the 80 general-purpose product terms can be grouped into 20 sets of four and sent into a product term sharing array (ptsa) which allows sharing up to a maximum of 28 product terms for a single function. alternatively, the ptsa can be by- passed for functions of four product terms or less. the 20 registered macrocells in the glb are driven by the 20 outputs from the ptsa or the ptsa bypass. each macrocell contains a programmable xor gate, a pro- grammable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. each macrocell has two outputs, one output can be fed back inside the glb to the and- array, while the other output drives both the big fast megablock routing pool and the global routing plane. this dual output capability from the macrocell allows efficient use of the hardware resources. one output can be a registered function for example, while the other output can be an unrelated combinatorial function. macrocell registers can be clocked from one of several global, local or product term clocks available on the device. a global, local and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers. reset and preset for the macrocell register is provided from both global and product term signals. the polarity of all of these control signals is selectable on an individual macrocell basis. the macro- cell register can be programmed to operate as a d-type register, a d-type flow-through latch or a t-type flip flop. the 20 outputs from the glb can drive both the big fast megablock routing pool within the big fast megablock and the global routing plane between the big fast megablocks. the big fast megablock routing pool con- tains general purpose tracks which interconnect the six glbs within the big fast megablock and dedicated tracks for the signals from the big fast megablock i/o cells. the global routing plane contains general pur- pose tracks that interconnect the big fast megablocks and also carry the signals from the i/os connected to the global routing plane. control signals for the i/o cell registers are generated using an extra product term within each glb, or using dedicated input pins. each glb has two extra product terms beyond the 80 available for the macrocell logic. the first additional product term is used as an optional shared product term clock for all the macrocells within the glb. the second additional product term is then routed to an i/o control bus using a separate routing structure from the big fast megablock routing pool and global routing plane. use of a separate control bus routing structure allows the i/o registers to have many control signals with no impact on the interconnection of the glbs and big fast megablocks. the i/o control bus is split into four quadrants, each servicing the i/o cell control re- quirements for one edge of the device. signals in the control bus can be independently selected by any or all i/o cells to act as clock, clock enable, output enable, reset or preset. each big fast megablock has 24 i/o cells. the global routing pool has 144 i/o cells. each i/o cell can be configured as a combinatorial input, combinatorial out- put, registered input, registered output or bidirectional i/o. i/o cell registers can be clocked from one of several global, local or product term clocks which are selected from the i/o control bus. a global and product term clock enable is also provided, eliminating the need for the user to gate the clock to the i/o cell registers. reset and preset for the i/o cell register is provided from both global and product term signals. the polarity of all of these control signals is selectable on an individual i/o cell basis. the i/o cell register can be programmed to operate as a d- type register or a d-type latch. the input thresholds are fixed at levels which comply with both 3.3v and 2.5v interfaces. the output driver can source 4ma and sink 8ma (3.3v output supply). the isplsi 8000v family description (continued)
specifications isplsi 8840v 4 output drivers have a separate vccio power supply which is independent of the main vcc supply for the device. this feature allows the output drivers to run from either 3.3v or 2.5v while the device logic is always powered from 3.3v. the output drivers also provide individually programmable edge rates and open drain capability. a programmable pullup resistor is provided to tie off unused inputs and a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by another device. the isplsi 8000v family features 3.3v, non-volatile in- system programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. programming is achieved through the industry standard ieee 1149.1-compliant boundary scan interface using the jtag protocol. bound- ary scan test is also supported through the same interface. an enhanced, multiple cell security scheme is provided that prevents reading of the jedec programming file when secured. after the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. isplsi 8840v description the isplsi 8840v device has seven big fast megablocks for a total of 7 x 120 = 840 macrocells. each big fast megablock has a total of 24 i/o cells and the global routing plane has a total of 144 i/o cells. this gives (7 x 24) + 144 = 312 i/os for the full i/o version, while the partial i/o version contains 72 big fast megablock i/os + 120 global i/os = 192 i/os. the total registers in the device is the sum of macrocells plus i/o cells, 840 + 312 = 1152 registers. embedded tristate bus there is a 108-line embedded internal tristate bus as part of the global routing plane (grp), enabling multiple glbs to drive the same tracks. this bus can be parti- tioned into various bus widths such as twelve 9-line buses, six 18-line buses or three 36-line buses. the glbs can dynamically share a subset of the global routing plane tracks. this feature eliminates the need to convert tristate buses to wide multiplexers on the pro- grammable device. up to 18 macrocells per glb can participate in driving the embedded tristate bus. the remaining two macrocells per glb are used to generate the internal tristate driver control signals on each data byte (with parity). the embedded tristate bus can also be configured as an extension of an external tristate bus using the bidirectional capability of the i/o cells con- nected to the global routing plane. the global routing plane i/os 0-8 and 15-23 from each group (i/ogx as defined in the i/o pin location table) can connect to the internal tristate bus as well as the unidirectional/non- tristate global routing channels. i/os 9-14 connect only to the global routing channel. the embedded tristate bus has internal bus hold and arbitration features in order to make the function more ?ser friendly.?the bus hold feature keeps the internal bus at the previously driven logic state when the bus is not driven to eliminate bus float. the bus arbitration is performed on a ?irst come, first served?priority. in other words, once a logic block drives the bus, other logic blocks cannot drive the bus until the first releases the bus. this arbitration feature prevents internal bus contention when there is an overlap between two bus enable sig- nals. typically, it takes about 3ns to resolve one bus signal coming off the bus to another bus signal driving the bus. the arbitration feature, combined with the predict- ability of the cpld, makes the embedded tristate bus the most practical for real world bus implementation. isplsi 8000v family description (continued)
specifications isplsi 8840v 5 0 pt 0 pt 1 pt 2 to output control mux pt 3 macrocell 0 macrocell 19 to interconnect to interconnect pt 8 pt 9 pt 10 pt 11 macrocell 2 to interconnect 20 pt 4 pt 5 pt 6 pt 7 macrocell 1 to interconnect feedback inputs 0 1 2 19 43 pt 76 pt 77 pt 78 pt 79 pt 81 pt 80 pt 12 pt 13 pt 14 pt 15 macrocell 3 to interconnect 3 ptsa bypass single pt pt clock pt preset pt reset from ptsa shared pt clock from tristate bus track bus input ptsa bypass single pt pt clock pt preset pt reset from ptsa shared pt clock from tristate bus track bus input ptsa bypass single pt pt clock pt preset pt reset from ptsa shared pt clock from tristate bus track bus input ptsa bypass single pt pt clock pt preset pt reset from ptsa shared pt clock from tristate bus track bus input ptsa bypass single pt pt clock pt preset pt reset from ptsa shared pt clock from tristate bus track bus input general purpose big fast megablock input tracks i/o big fast megablock input tracks and array input routing fully populated and array product term sharing array function selector (e 2 cell controlled) note: macrocells 9 and 10 do not support tristate bus feedback. figure 2. isplsi 8000v glb overview
specifications isplsi 8840v 6 figure 3. isplsi 8000v macrocell overview ptsa dq rp feedback to and array ptsa bypass single pt global clock 0 global clock 1 global clock 2 pt clock grst pt reset pt preset from pt80 clk en global clock enable r/l : function selector (e 2 cell controlled) *not available for macrocells 9 and 10. bus input from tristate bus track* grst reset pin preset/reset input has global polarity control to all macrocells and i/o cells to big fast megablock or global interconnect to specific global tristate bus* from macrocell 9 or 10
specifications isplsi 8840v 7 dq r slew rate open drain big fast megablock i/o pad or global i/o pad p clken global i/o clock enable global clock 0 global clock 2 quadrant i/o clock grst global oe0 toe r/l multiplexed output from big fast megablock or global track global oe1 global oe2 global oe3 vccio : function selector (e 2 cell controlled) vccio vccio to specific big fast megablock or global tracks to specific global tristate bus from output control bus global i/o cell only from output control bus from output control bus from output control bus from output control bus figure 4. isplsi 8000v i/o cell
specifications isplsi 8840v 8 output control organization in addition to the data input and output to the i/o cells, each i/o cell can have up to six different i/o cell control signals. in addition to the internal oe control, the five control signals for each i/o cell consist of pin oe control, clock enable, clock input, asynchronous preset and asyn- chronous reset. all of the i/o control signals can be driven either from the dedicated external input pins or from the internal control bus. the output enable of each i/o cell can be driven by 21 different sources 16 from the output control bus, four from the global oe pins and one from the test oe pin. figure 5. output control bus and quadrant organization q u a d ra n t 0 , 1 6 -b it w id e o u tp u t c o n tro l b u s (i/o b 0 -b 6 < 0 -1 1 > , q io c l k 0 ) q u a d ra n t 2 , 1 6 -b it w id e o u tp u t c o n tro l b u s (i/o b 0 -b 6 < 1 2 -2 3 > , q io c l k 2 ) q u a d ra n t 1 , 1 6 -b it w id e o u tp u t c o n tr o l b u s (i/o g 0 -g 5 < 1 2 -2 3 > , q io c l k 1 ) q u a d r a n t 3 , 1 6 -b it w id e o u tp u t c o n tro l b u s (i/o g 0 -g 5 < 0 - 1 1 > , q io c l k 3 ) g l b g e n e ra te d o u tp u t c o n tro l (se e f ig u re 2 ) f ro m p t 8 1 oe bus.eps the global oe signals and test oe signal are driven from the dedicated external control input pins. the 16-bit wide output control buses are organized in four different quadrants as shown in figure 5. since each glb is capable of generating the output control signals, each of the output control bus signals can be driven from a unique glb. the 42 glbs can generate a total of 42 unique i/o control signals. referring to figure 2, the glb generates its output control signal from control product term (pt81). figure 5 also illustrates how the quadrant clocks are routed to the appropriate quadrant i/o cells.
specifications isplsi 8840v 9 figure 6. boundary scan register circuit for i/o pins figure 7. boundary scan register circuit for input-only pins normal function oe extest update dr scanout (to next cell) clock dr scanin (from previous cell) shift dr *internal power-up reset signal. not connected to external reset pin. normal function toe dq dq dq dq dq i/o pin reset* bscan registers bscan latches highz 0 0 1 1 prog_mode prog_mode extest scanout (to next cell) clock dr scanin (from previous cell shift dr dq input pin
specifications isplsi 8840v 10 figure 8. boundary scan waveforms and timing specifications tms tdi tck tdo data to be captured data to be driven out valid data valid data valid data valid data data captured btsu t bth t btcl t btch t btcp t btvo t btco t btoz t btcpsu t btcph t btuov t btuco t btuoz t symbol table 2-0010/8840v parameter t btch t btcl t btsu t bth tck pulse width high tck pulse width low tdi, tms setup time to tck tdi, tms hold time from tck ns t btcp tck clock pulse width ns ns ns ns max units 50 100 50 25 25 t btco t btvo t btcpsu t btcph tap controller, tck to tdo valid tap controller, tck to tdo high-impedance to valid output bscan test capture register setup time bscan test capture register hold time 25 ns t rf tck, tdi, tms rise and fall time mv/ns 25 ns ns ns t btoz tap controller, tck to tdo high-impedance 25 ns 50 25 25 t btuco t btuoz t btuov bscan test update register clock to valid output bscan test update register clock to high-impedance bscan test update register high-impedance to valid output 65 65 ns ns ns 65 min
specifications isplsi 8840v 11 absolute maximum ratings 1,2 supply voltage v cc .................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v tri-stated output voltage applied ........... -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). 2. compliance with the thermal management section of the lattice semiconductor data book or cd-rom is a requirement. dc recommended operating condition capacitance (t a =25 c,f=1.0 mhz) erase/reprogram specification symbol table 2-0005/8840v v ccio parameter i/o supply voltage min. max. units 2.3 3.6 v a v cc supply voltage commercial t = 0 c to 70 c3.03.6v symbol table 2-0006/8840v c parameter clock capacitance 10 units typical test conditions 2 pf v = 3.3v, v = 2.0v cc ck c global input capacitance 10 3 pf v = 3.3v, v = 2.0v cc g c i/o capacitance 10 1 pf v = 3.3v, v = 2.0v cc i/o table 2-0008/8840v parameter minimum maximum units erase/reprogram cycles 10000 cycles
specifications isplsi 8840v 12 switching test conditions figure 9. test load output load conditions (see figure 9) over recommended operating conditions dc electrical characteristics for 3.3v range input pulse levels table 2-0003/8840v input rise and fall time input timing reference levels ouput timing reference levels output load gnd to vccio min 1.5v 1.5v see figure 9 3-state levels are measured 0.5v from steady-state active level. 1.5 ns 10% to 90% test condition r1 r2 3.3v 2.5v cl a 316 ? 348 ? 35pf b 348 ? 35pf 316 ? 35pf active high active low c d slow slew 316 ? 5pf 348 ? r1 r2 511 ? 475 ? 475 ? 511 ? 511 ? ? 35pf ? 475 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004a/8840v r 1 v ccio r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a/8840v v ol symbol table 2-0007/8840v v oh v ih parameter output low voltage output high voltage input high voltage i = 8 ma i = -4 ma ol oh condition min. max. units 2.4 2.0 0.4 5.25 v v v v il input low voltage -0.3 0.8 v v ccio i/o supply voltage 3.0 3.6 v t a = 0 c to + 70 c over recommended operating conditions dc electrical characteristics for 2.5v range table 2-0007b/8840v symbol v ih parameter input high voltage condition min. max. units 1.7 5.25 v v il input low voltage t a = 0 c to + 70 c -0.3 0.7 v v ccio i/o supply voltage 2.3 2.7 v v oh output high voltage v ccio=min , v in =v ih or v il , i oh = -2ma v ccio=min , v in =v ih or v il , i ol = 2ma 1.7 v v ccio=min , v in =v ih or v il , i oh = -100 a 2.1 v 0.7 v v ccio=min , v in =v ih or v il , i ol = 100 a 0.2 v v ol output low voltage
specifications isplsi 8840v 13 over recommended operating conditions dc electrical characteristics symbol 1. measured at a frequency of 1mhz using 42 20-bit counters. 2. typical values are at v cc = 3.3v and t a = 25 c. 3. maximum i cc varies widely with specific device configuration and operating frequency. 4. pullup is capable of pulling minimum voltage of v oh under no-load conditions. 5. unused inputs held at gnd. table 2-0007c/8840v i pu i bhl parameter i bhh i bhlo 1,3,5 4 i cc i/o active pullup current bus hold low sustaining current bus hold high sustaining current bus hold low overdrive current operating power supply current v = 0.5v, v = 3.0v f = 1 mhz i ih i il input or i/o high leakage current input or i/o low leakage current 0v v v (max.) in il toggle il ih condition min. typ. max. units 2 40 -40 460 -10 10 -250 50 550 a a a a a a i bhlh i bht bus hold high overdrive current bus hold trip points v il -550 v ih a v a ma high speed mode 220 low power mode (v ccio -0.2)v v in v ccio v ccio v in 5.25v 0v v in v il 0v v in v ccio 0v v in v ccio v in = v il(max) v in = v ih(min)
specifications isplsi 8840v 14 t pd1 units -90 -60 min. test cond. table 2-0030/8840v max. description # para- meter a 1 prop delay, bfm input to same bfm output, 4 pt bypass 10.0 ns t pd2 a 2 prop delay, global input to global output ns t suq 4 i/o cell reg, data setup time, quadrant i/o clock 8.0 ns t hq 5 i/o cell reg, data hold time, quadrant i/o clock ns t coq a 6 i/o cell reg, quadrant clock to output delay 6.0 ns t sug 7 i/o cell reg, data setup time, global clock ns t hg 8 i/o cell reg, data hold time, global clock ns t cog a 9 i/o cell reg, global clock to output delay 7.5 ns t su1 10 glb reg setup, bfm input to same bfm glb, 4 pt bypass ns t h1 11 glb reg hold time, bfm input to same bfm glb 0.0 ns t co1 a 12 glb reg, global clock to same bfm output delay 10.0 ns t suceq 13 i/o cell reg, clken setup time, quadrant i/o clock 6.5 ns t hceq 14 i/o cell reg, clken hold time, quadrant i/o clock 0.0 ns t suceg 15 glb reg, clken setup time, global clock 4.5 ns t hceg 16 glb reg, clken hold time, global clock 0.0 ns t goe b/c 17 global output enable/disable delay ns t rglb 18 global reset/preset time, glb reg 15.0 ns t rio 19 global reset/preset time, i/o cell reg 10.0 ns t rw 20 global reset/preset pulse duration 6.5 ns 0.0 6.0 7.0 16.0 13.5 10.0 0.0 t wh 21 global or quadrant clock pulse, high duration 6.0 ns t wl 22 global or quadrant clock pulse, low duration 6.0 ns f max 3 clk frequency, local feedback, same glb 90.0 15.0 12.0 9.0 11.0 0.0 15.0 9.5 0.0 6.5 0.0 22.0 15.0 9.5 0.0 9.0 10.0 24.0 15.0 0.0 9.0 9.0 60.0 mhz -125 min. max. min. max. 8.5 5.0 4.0 6.0 0.0 8.0 5.5 0.0 3.5 0.0 14.0 8.5 5.0 0.0 3.5 4.5 7.0 0.0 4.0 4.0 125.0 1. unless noted otherwise, all parameters use ptsa and clk0. 2. refer to timing model in this data sheet for further details. 3. standard 20-bit counter with local feedback. 4. refer to switching test conditions section. 4 2 3 external switching characteristics 1 over recommended operating conditions
specifications isplsi 8840v 15 internal timing parameters over recommended operating conditions i/o cell delay t idcom 23 input pad and input buffer, combinatorial input 0.3 0.4 0.6 ns t idreg 24 input pad and input buffer, registered input 6.4 7.6 11.2 ns t obp 25 output register/latch bypass to output buffer 0.0 0.0 0.0 ns t ibp 26 input register/latch bypass to bfm routing or grp 0.4 0.5 0.8 ns t iolat 27 i/o cell latch, transparent mode 2.0 2.4 3.6 ns t ioco 28 i/o cell register/latch, clk/gate to output 0.5 1.2 1.6 ns t iosu 29 i/o cell register/latch, setup time 0.5 2.4 3.9 ns t ioh 30 i/o cell register/latch, hold time 2.5 3.2 4.7 ns t iorst 31 i/o cell register/latch, reset or set time 1.5 1.7 2.5 ns t iosuce 32 i/o cell regi ster/latch, setup time for clk enable 0.9 1.0 1.2 ns t iohce 33 i/o cell regi ster/latch, hold time for clk enable 4.6 4.6 6.9 ns t odreg 34 i/o cell output buffer delay, registered output 1.6 1.9 2.9 ns t odcom 35 i/o cell o utput buffer delay, combinatorial output 1.6 1.9 2.9 ns t odz 36 output driver disable time 1.4 1.7 2.6 ns t slf 37 slew rate adder, fast slew rate 0.0 0.0 0.0 ns t sls 38 slew rate adder, slow slew rate 6.2 7.3 10.9 ns glb / macrocell delay t andhs 39 and array, high speed mode 2.6 2.9 4.2 ns t andlp 40 and array, low power mode 6.5 7.7 11.5 ns t 1pt 41 single product term bypass 1.9 2.2 3.4 ns t 4ptcom 42 four product term bypass, combinatorial macrocell 0.5 0.6 0.9 ns t 4ptreg 43 four product term bypass, registered macrocell 1.4 1.7 2.2 ns t ptsa 44 product term sharing array 2.4 2.7 4.1 ns t mbp 45 macrocell register/latch bypass 0.0 0.0 0.0 ns t mlat 46 macrocell latch, transparent mode 4.6 5.5 8.2 ns t mco 47 macrocell register/latch, clk/gate to output 0.2 0.8 0.9 ns t msu 48 macrocell register/latch, setup time 2.7 4.5 6.9 ns t mh 49 macrocell register/latch, hold time 1.0 1.2 1.1 ns t mrst 50 macrocell register/latch, reset or set time 2.0 1.5 1.6 ns t msuce 51 m acrocell register/latch, setup time for clk enable 1.0 1.3 1.7 ns t mhce 52 macrocell register/latch, hold time for clk enable 2.3 2.6 3.9 ns t floc 54 local feedback to and array 0.1 0.1 0.6 ns t pck 55 single product term, clk 1.3 1.3 1.6 1.6 2.5 2.5 ns t pcken 56 single product term, clk enable 1.7 2.0 3.1 ns t sck 57 shared product term, clk 1.7 1.9 2.0 2.3 3.1 3.5 ns t scken 58 shared product term, clk enable 1.7 1.9 2.0 2.3 3.1 3.5 ns t prst 59 single product term, reset or set delay 1.5 1.7 2.6 ns t rdir 60 macrocell register, direct input from grp 7.2 8.4 12.7 ns -125 -90 -60 min max min max min max units para- meter # 2 description
specifications isplsi 8840v 16 internal timing parameters over recommended operating conditions bfm / global routing pool delay t bfmi 61 bfm routing delay, signal from i/o cell 0.4 1.0 0.6 1.3 0.8 1.9 ns t grpi 62 grp delay, signal from i/o cell 1.6 1.9 2.8 ns t grpiz 63 internal tristate bus enable/disable, i/o cell buffer 4.1 4.9 7.3 ns t bfmm 64 bfm routing delay, signal from macrocell 0.6 0.7 1.1 ns t grpm 65 grp delay, signal from macrocell 2.0 3.0 4.5 ns t grpmz 66 internal tristate bus enable/disable, macrocell buffer 3.0 4.3 6.5 ns t bfmg 67 bfm routing delay, signal from grp 2.5 3.3 4.9 ns t grpb 68 grp delay, signal from bfm routing 1.3 1.5 2.3 ns t bcom 69 bfm routing to i/o cell, combinatorial path 1.5 1.7 2.6 ns t breg 70 bfm routing to i/o cell, registered path 2.3 2.6 4.0 ns t gcom 71 grp to i/o cell, combinatorial path 0.8 0.8 1.2 ns t greg 72 grp to i/o cell, registered path 1.6 1.7 2.6 ns i/o control bus delay t piock 73 product term as i/o cell register clock 4.1 4.7 7.2 ns t piocken 74 product term as i/o cell register clock enable 4.6 5.3 8.1 ns t poe 75 product term as output buffer enable/disable 5.6 6.5 9.9 ns t piorst 76 product term as i/o cell register reset or set delay 4.3 5.0 7.6 ns t pioz 77 internal tristate bus control signal for i/o cell buffer 3.3 3.8 5.8 ns global control delay t gck 78 global macrocell register clk 3.9 4.1 4.3 4.9 6.6 7.5 ns t gcken 79 global macrocell register clk enable 6.4 6.4 7.5 7.5 11.4 11.4 ns t giock 80 global i/o register clk 3.4 3.9 4.0 4.4 6.1 6.5 ns t giocken 81 global i/o register clk enable 6.5 6.5 7.5 7.5 11.4 11.4 ns t qck 82 quadrant i/o register clk 1.9 1.9 2.0 2.9 3.1 4.5 ns t goe 83 global output enable 5.6 8.3 12.4 ns t toe 84 test output enable 8.5 10.1 15.2 ns t gmrst 85 global glb register reset 7.6 7.8 11.8 ns t giorst 86 global i/o cell register reset 5.4 6.4 9.6 ns 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. -125 -90 -60 min max min max min max units para- meter # 2 description
specifications isplsi 8840v 17 isplsi 8840v timing model i/o register delays bfm routing pool output routing output buffer delays output slew rate adders i/o pad and array ptsa macrocell register i/o pad input pad 8840v_model.eps t slf t #37, #38, sls t odreg t odcom t #34, #35, #36, odz t bcom t breg t gcom t #69, #70, #71, #72, greg t obp #25, t ibp #26, t iolat #27, t ioco #28, t iosu #29, t ioh #30, t iosuce #32, t iohce #33, t #31, iorst t #23, idcom t #24, idreg t #61, bfmi t #67, bfmg t #64, bfmm t grpi t grpiz t grpm t grpmz t #62, #63, #65, #66, #68, grpb t andhs t andlp t 1pt t 4ptcom t 4ptreg t #41, #42, #43, #44, ptsa t mbp t mlat t mco t msu t mh t mrst t msuce t #45, #46, #47, #48, #49, #50, #51, #52, mbce t giock #80, #39, #40, t giocken #81, t qck #82, t giorst #86, t gck #78, t gcken #79, t gmrst #85, t goe #83, t #84, toe t pck t pcken t sck t scken t #55, #56, #57, #58, #59, prst t #54, floc t #60, rdir glb/ macrocell global routing plane pt mcell controls local feedback bus direct input buffer and i/o cell register output path input path z t piock t piocken t poe t piorst t #73, #74, #75, #76, #77, pioz pt i/o control bus input buffer delays global control delay
specifications isplsi 8840v 18 example timing calculations t pd1 = (bfm input path delay) + (glb delay) + (output path delay) = ( t idcom + t ibp + t bfmi max) + ( t andhs + t 4ptcom + t mbp) + ( t bfmm + t bcom + t obp + t odcom + t slf) = (#23 + #26 + #61) + (#39 + #42 + #45) + (#64 + #69 + #25 + #35 + #37) = (0.3 + 0.4 + 1.0) + (2.6 + 0.5 + 0.0) + (0.6 + 1.5 + 0.0 + 1.6 + 0.0) = 8.5 ns t pd (within bfm) = (bfm delay) + (glb delay) = ( t bfmm) + ( t andhs + t 4ptcom + t mbp) = (#64) + (#39 + #42 + #45) = (0.6) + (2.6 + 0.5 + 0.0) = 3.7 ns t pd (between bfms) = (grp delay) + (bfm delay) + (glb delay) = ( t grpm) + ( t bfmg) + ( t andhs + t 4ptcom + t mbp) = (#65) + (#67) + (#39 + #42 + #45) = (2.0) + (2.5) + (2.6 + 0.5 + 0.0) = 7.6 ns bfm i/o to internal tri-state enable/disable = (bfm input path delay) + (glb delay, 1pt) + (tri-state control delay) = ( t idcom + t ibp + t bfmi max) + ( t andhs + t 1pt + t mbp) + ( t grpmz) = (#23 + #26 + #61) + (#39 + #41 + #45) + (#66) = (0.3 + 0.4 + 1.0) + (2.6 + 1.9 + 0.0) + (3.0) = 9.2 ns t su1 = (bfm input path delay) + (glb setup time) - (min. global clock delay) = ( t idcom + t ibp + t bfmi max) + ( t andhs + t 4ptreg + t msu) ( t gck min) = (#23 + #26 + #61) + (#39 + #43 + #48) (#78) = (0.3 + 0.4 + 1.0) + (2.6 + 1.4 + 2.7) (3.9) = 4.5 ns 1/ f max = (global clk to mc output) + (local feedback) + (glb setup time) = ( t mco) + ( t floc) + ( t andhs + t ptsa + t msu) = (#47) + (#54) + (#39 + #44 + #48) = (0.2) + (0.1) + (2.6 + 2.4 + 2.7) = 8.0 ns f max = 125 mhz note: calculations are based upon timing specifications for the isplsi 8840v-125l
specifications isplsi 8840v 19 power consumption power consumption in the isplsi 8840v device depends on two primary factors: the speed at which the device is operating and the number of product terms used. the product terms have a fuse-selectable speed/power tradeoff setting. each group of four product terms has a single speed/power tradeoff control fuse that acts on the complete group of four. the fast high-speed setting 0127/8840v the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. i cc can be estimated for the isplsi 8840v using the following equation: i cc = 35.0 + (# of turbo pts *0.25) + (# of non-turbo pts * 0.11) + (# of macrocells used * fmax * af * 0.041) # of turbo pts = number of turbo product terms used in design # of non-turbo pts = number of non-turbo product terms used in design fmax = maximum operating frequency average macrocell toggle frequency note: an activity factor of 1.0 means all macrocell registers toggle at fmax. an activity factor of 0.5 means the average macrocell register toggles at half of fmax. fmax af (activity factor) = f max (mhz) i cc (ma) notes: configuration of 42 20-bit counters typical current at 3.3v, 25 c 700 600 500 400 300 200 100 0 800 0 102030405060708090100 turbo non-turbo 110 isplsi 8840v 120 130 figure 10. typical device power consumption vs fmax operates product terms at their normal full power con- sumption. for portions of the logic that can tolerate longer propagation delays, selecting the slower low- power setting will significantly reduce the power dissipation for these product terms. figure 10 shows the relationship between power and operating speed.
specifications isplsi 8840v 20 clk0, clk1, dedicated clock input for the glb registers only. these clock inputs are connected to one of the clock clk2 inputs of all glb registers in the device. clken dedicated clock enable input for the glb registers only. this input is available as a clock enable for each glb register in the device. use of the clock enable input eliminates the need for the user to gate the clock to the register. gnd ground (gnd) goe0, goe1, global output enable inputs. goe2, goe3 set/reset dedicated, reset/preset pin connected to all registers in the device, glb registers and i/o registers. each register can independently choose to be reset or preset when this signal goes active. the active polarity is user selectable. ioclken dedicated clock enable input for the i/o registers only. this input is available as a clock enable input for all i/o registers in the device. use of the clock enable input eliminates the need for the user to tie the clock to the i/o register. i/o input/output these are the general purpose i/o used by the logic array. epen embedded port enable pin when this pin is high, the port is enabled. when this pin is low, the state machine is held at reset asynchronously and tck, tms and tdi are ignored. tms input this signal is the test mode select input signal. qioclk0, dedicated clock inputs for the i/o registers only. these clock inputs are connected to the i/o registers qioclk1, on the same side of the device only, they are not connected to all of the i/o registers. use of these qioclk2, quadrant i/o clocks gives the fastest tco from the device. qioclk3 tck input this signal is the test clock input signal. tdi input this signal is the test data input signal. tdo output this signal is the test data out output signal. toe test output enable. tristates all i/o pins when a logic low is driven. vcc vcc vccio power supply for the output drivers. the internal logic of the device is connected to vcc which is always 3.3v. the output drivers are connected to vccio which can be equal to vcc or 2.5v. this allows the output drivers to be powered from 2.5v, for example, to interface directly with another 2.5v device. nc 1 no connect. signal descriptions signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 8840v 21 qioclk0, qioclk1, qioclk2, qioclk3 clk0, clk1, clk2 clken ioclken epen tck tdi tdo tms goe0, goe1, goe2, goe3 toe set/reset vcc vccio gnd nc 1 signal locations ae14, p22, a15, n3 ac15, r24, b15 ab17 e16 b26 a2 af1 b3 ac4 af15, p23, d16, n5 l5 p2 e9, e12, e15, e18, f5, f10, f17, f22, g5, g22, k5, k22, l22, m5, n22, p5, r22, t5, u5, u22, y5, y22, aa5, aa10, aa17, aa22, ab9, ab12, ab15, ab18 e8, e13, e19, e20, f7, f8, f20, j6, j21, k3, l24, n1, p24, t3, u25, v6, y23, aa7, aa8, aa20, ab8, ab14, ab19, ab20 e5, e11, e14, e22, f6, f21, l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, aa6, aa21, ab5, ab13, ab16, ab22 a1, a16, b1, b2, c1, c2, c3, c24, c25, c26, d1, d2, d3, d4, d24, d25, d26, e6, e17, e21, e23, e24, e25, e26, f9, f18, g6, g21, y6, y21, aa9, aa18, ab1, ab2, ab3, ab4, ab6, ab10, ab21, ab23, ac1, ac2, ac3, ac23, ac24, ac25, ac26, ad1, ad2, ad3, ad15, ad25, ad26, ae1, ae25, ae26, af25, af26 signal name 1. nc pins are not to be connected to any active signals, vcc or gnd. 272-ball bga 492-ball bga y8, m20, c8, n2 y9, p18, d8 v9 b9 c17 a4 u5 c4 w4 y10, m19, c9, n1 l3 p3 d9, d10, d11, d12, j4, j17, k4, k17, l4, l17, m4, m17, u9, u10, u11, u12 a7, a8, a20, b16, c5, c12, e4, g20, h4, m1, n17, u2, u20, v2, v6, w7, w8, w16, w19, y13 d4, d16, d17, j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12, u4, u17 a9, w9, v17
specifications isplsi 8840v 22 i/o pin locations (272-ball bga package) signal bga signal bga signal bga signal bga i/o g0 <0> v4 i/o g0 <1> y3 i/o g0 <2> y2 i/o g0 <3> w3 i/o g0 <4> y1 i/o g0 <5> w2 i/o g0 <6> w1 i/o g0 <7> v3 i/o g0 <8> v1 i/o g0 <9> u3 i/o g0 <10> r4 i/o g0 <11> t4 i/o g0 <12> u19 i/o g0 <13> r17 i/o g0 <14> v20 i/o g0 <15> v19 i/o g0 <16> u18 i/o g0 <17> v18 i/o g0 <18> t17 i/o g0 <19> w20 i/o g0 <20> y20 i/o g0 <21> y19 i/o g0 <22> w18 i/o g0 <23> y18 i/o g2 <0> u1 i/o g2 <1> t3 i/o g2 <2> t2 i/o g2 <3> t1 i/o g2 <4> r3 i/o g2 <5> r2 i/o g2 <6> r1 i/o g2 <7> p4 i/o g2 <8> p2 i/o g2 <9> n4 i/o g2 <10> n3 i/o g2 <11> p1 i/o g2 <12> n18 i/o g2 <13> n19 i/o g2 <14> n20 i/o g2 <15> p19 i/o g2 <16> p17 i/o g2 <17> p20 i/o g2 <18> r20 i/o g2 <19> r19 i/o g2 <20> r18 i/o g2 <21> t20 i/o g2 <22> t19 i/o g2 <23> t18 i/o g3 <0> h2 i/o g3 <1> h1 i/o g3 <2> j3 i/o g3 <3> j2 i/o g3 <4> j1 i/o g3 <5> k3 i/o g3 <6> k2 i/o g3 <7> k1 i/o g3 <8> l2 i/o g3 <9> l1 i/o g3 <10> m2 i/o g3 <11> m3 i/o g3 <12> m18 i/o g3 <13> l20 i/o g3 <14> l19 i/o g3 <15> l18 i/o g3 <16> k20 i/o g3 <17> k19 i/o g3 <18> k18 i/o g3 <19> j20 i/o g3 <20> h20 i/o g3 <21> j19 i/o g3 <22> h19 i/o g3 <23> j18 i/o g4 <0> g2 i/o g4 <1> g1 i/o g4 <2> h3 i/o g4 <3> g3 i/o g4 <4> g4 i/o g4 <5> f3 i/o g4 <6> f1 i/o g4 <7> f2 i/o g4 <8> f4 i/o g4 <9> e1 i/o g4 <10> e2 i/o g4 <11> e3 i/o g4 <12> d20 i/o g4 <13> f17 i/o g4 <14> e19 i/o g4 <15> g17 i/o g4 <16> g18 i/o g4 <17> f18 i/o g4 <18> e20 i/o g4 <19> f19 i/o g4 <20> h17 i/o g4 <21> f20 i/o g4 <22> h18 i/o g4 <23> g19 i/o g5 <0> a3 i/o g5 <1> b2 i/o g5 <2> b3 i/o g5 <3> a2 i/o g5 <4> a1 i/o g5 <5> b1 i/o g5 <6> d3 i/o g5 <7> d2 i/o g5 <8> c3 i/o g5 <9> c2 i/o g5 <10> d1 i/o g5 <11> c1 i/o g5 <12> d19 i/o g5 <13> e18 i/o g5 <14> c20 i/o g5 <15> b20 i/o g5 <16> a19 i/o g5 <17> c19 i/o g5 <18> d18 i/o g5 <19> b19 i/o g5 <20> c18 i/o g5 <21> e17 i/o g5 <22> b18 i/o g5 <23> a18 i/o b0 <0> y4 i/o b0 <1> v5 i/o b0 <2> w5 i/o b0 <3> y5 i/o b0 <4> u6 i/o b0 <5> u7 i/o b0 <6> w6 i/o b0 <7> v7 i/o b0 <8> y6 i/o b0 <9> y7 i/o b0 <10> u8 i/o b0 <11> v8 i/o b0 <12> b8 i/o b0 <13> c7 i/o b0 <14> d7 i/o b0 <15> b7 i/o b0 <16> b6 i/o b0 <17> c6 i/o b0 <18> a6 i/o b0 <19> d6 i/o b0 <20> b5 i/o b0 <21> a5 i/o b0 <22> d5 i/o b0 <23> b4 i/o b4 <0> v10 i/o b4 <1> w10 i/o b4 <2> y11 i/o b4 <3> w11 i/o b4 <4> v11 i/o b4 <5> y12 i/o b4 <6> w12 i/o b4 <7> v12 i/o b4 <8> w13 i/o b4 <9> u13 i/o b4 <10> v13 i/o b4 <11> y14 signal bga i/o b4 <12> b14 i/o b4 <13> d13 i/o b4 <14> b13 i/o b4 <15> a13 i/o b4 <16> a12 i/o b4 <17> b12 i/o b4 <18> b11 i/o b4 <19> a11 i/o b4 <20> c11 i/o b4 <21> b10 i/o b4 <22> a10 i/o b4 <23> c10 i/o b6 <0> w14 i/o b6 <1> v14 i/o b6 <2> u14 i/o b6 <3> y15 i/o b6 <4> w15 i/o b6 <5> v15 i/o b6 <6> u15 i/o b6 <7> y16 i/o b6 <8> v16 i/o b6 <9> u16 i/o b6 <10> w17 i/o b6 <11> y17 i/o b6 <12> b17 i/o b6 <13> a17 i/o b6 <14> c16 i/o b6 <15> d15 i/o b6 <16> c15 i/o b6 <17> a16 i/o b6 <18> b15 i/o b6 <19> d14 i/o b6 <20> c14 i/o b6 <21> a15 i/o b6 <22> a14 i/o b6 <23> c13
specifications isplsi 8840v 23 i/o pin locations (492-ball bga package) signal bga signal bga signal bga signal bga signal bga i/o g0 <0> aa4 i/o g0 <1> aa3 i/o g0 <2> aa2 i/o g0 <3> aa1 i/o g0 <4> y4 i/o g0 <5> y3 i/o g0 <6> y2 i/o g0 <7> y1 i/o g0 <8> w4 i/o g0 <9> w3 i/o g0 <10> w2 i/o g0 <11> u6 i/o g0 <12> u21 i/o g0 <13> y26 i/o g0 <14> y25 i/o g0 <15> y24 i/o g0 <16> v21 i/o g0 <17> aa26 i/o g0 <18> aa25 i/o g0 <19> aa24 i/o g0 <20> aa23 i/o g0 <21> ab26 i/o g0 <22> ab25 i/o g0 <23> ab24 i/o g1 <0> t2 i/o g1 <1> w5 i/o g1 <2> u1 i/o g1 <3> u2 i/o g1 <4> u3 i/o g1 <5> u4 i/o g1 <6> v1 i/o g1 <7> v5 i/o g1 <8> v2 i/o g1 <9> v3 i/o g1 <10> v4 i/o g1 <11> w1 i/o g1 <12> w23 i/o g1 <13> w24 i/o g1 <14> w25 i/o g1 <15> w26 i/o g1 <16> v22 i/o g1 <17> v23 i/o g1 <18> v24 i/o g1 <19> v25 i/o g1 <20> v26 i/o g1 <21> w22 i/o g1 <22> u23 i/o g1 <23> u24 i/o g2 <0> t4 i/o g2 <1> t1 i/o g2 <2> w6 i/o g2 <3> r2 i/o g2 <4> r1 i/o g2 <5> r3 i/o g2 <6> r4 i/o g2 <7> r5 i/o g2 <8> p1 i/o g2 <9> p3 i/o g2 <10> p4 i/o g2 <11> n4 i/o g2 <12> p26 i/o g2 <13> p25 i/o g2 <14> r23 i/o g2 <15> t22 i/o g2 <16> r26 i/o g2 <17> r25 i/o g2 <18> t26 i/o g2 <19> t23 i/o g2 <20> w21 i/o g2 <21> t24 i/o g2 <22> t25 i/o g2 <23> u26 i/o g3 <0> k2 i/o g3 <1> k1 i/o g3 <2> l2 i/o g3 <3> h6 i/o g3 <4> l3 i/o g3 <5> l4 i/o g3 <6> l1 i/o g3 <7> m2 i/o g3 <8> m1 i/o g3 <9> m3 i/o g3 <10> m4 i/o g3 <11> n2 i/o g3 <12> n23 i/o g3 <13> n24 i/o g3 <14> n26 i/o g3 <15> n25 i/o g3 <16> m22 i/o g3 <17> m23 i/o g3 <18> m24 i/o g3 <19> m26 i/o g3 <20> h21 i/o g3 <21> m25 i/o g3 <22> l26 i/o g3 <23> l23 i/o g4 <0> k4 i/o g4 <1> h5 i/o g4 <2> j1 i/o g4 <3> j2 i/o g4 <4> j3 i/o g4 <5> j4 i/o g4 <6> h1 i/o g4 <7> j5 i/o g4 <8> h2 i/o g4 <9> h3 i/o g4 <10> h4 i/o g4 <11> k6 i/o g4 <12> h26 i/o g4 <13> j23 i/o g4 <14> j24 i/o g4 <15> j25 i/o g4 <16> j22 i/o g4 <17> j26 i/o g4 <18> k23 i/o g4 <19> k24 i/o g4 <20> k25 i/o g4 <21> h22 i/o g4 <22> k26 i/o g4 <23> l25 i/o g5 <0> e4 i/o g5 <1> e3 i/o g5 <2> e2 i/o g5 <3> e1 i/o g5 <4> f4 i/o g5 <5> f3 i/o g5 <6> f2 i/o g5 <7> f1 i/o g5 <8> g4 i/o g5 <9> g3 i/o g5 <10> g2 i/o g5 <11> g1 i/o g5 <12> k21 i/o g5 <13> h25 i/o g5 <14> h24 i/o g5 <15> h23 i/o g5 <16> g26 i/o g5 <17> g25 i/o g5 <18> g24 i/o g5 <19> g23 i/o g5 <20> f26 i/o g5 <21> f25 i/o g5 <22> f24 i/o g5 <23> f23 i/o b0 <0> ae2 i/o b0 <1> af2 i/o b0 <2> ae3 i/o b0 <3> af3 i/o b0 <4> ad4 i/o b0 <5> ae4 i/o b0 <6> af4 i/o b0 <7> ac5 i/o b0 <8> ad5 i/o b0 <9> ae5 i/o b0 <10> ab7 i/o b0 <11> af5 i/o b0 <12> b6 i/o b0 <13> e7 i/o b0 <14> c6 i/o b0 <15> d6 i/o b0 <16> a5 i/o b0 <17> b5 i/o b0 <18> c5 i/o b0 <19> d5 i/o b0 <20> a4 i/o b0 <21> b4 i/o b0 <22> c4 i/o b0 <23> a3 i/o b1 <0> ac6 i/o b1 <1> ad6 i/o b1 <2> ae6 i/o b1 <3> af6 i/o b1 <4> ac7 i/o b1 <5> ad7 i/o b1 <6> ae7 i/o b1 <7> af7 i/o b1 <8> ac8 i/o b1 <9> ad8 i/o b1 <10> ae8 i/o b1 <11> af8 i/o b1 <12> b9 i/o b1 <13> c9 i/o b1 <14> d9 i/o b1 <15> a8 i/o b1 <16> b8 i/o b1 <17> c8 i/o b1 <18> d8 i/o b1 <19> a7 i/o b1 <20> b7 i/o b1 <21> c7 i/o b1 <22> d7 i/o b1 <23> a6 i/o b2 <0> ac9 i/o b2 <1> ad9 i/o b2 <2> ae9 i/o b2 <3> af9 i/o b2 <4> ac10 i/o b2 <5> ad10 i/o b2 <6> ae10 i/o b2 <7> af10 i/o b2 <8> ae11 i/o b2 <9> ad11 i/o b2 <10> ab11 i/o b2 <11> ac11 i/o b2 <12> a12 i/o b2 <13> e10 i/o b2 <14> b12 i/o b2 <15> a11 i/o b2 <16> d11 i/o b2 <17> c11 i/o b2 <18> b11 i/o b2 <19> a10 i/o b2 <20> b10 i/o b2 <21> c10 i/o b2 <22> d10 i/o b2 <23> a9 i/o b3 <0> af11 i/o b3 <1> ae12 i/o b3 <2> af12 i/o b3 <3> ad12 i/o b3 <4> ac12 i/o b3 <5> ae13 i/o b3 <6> af13 i/o b3 <7> ad13 i/o b3 <8> ac13 i/o b3 <9> ac14 i/o b3 <10> ad14 i/o b3 <11> af14 i/o b3 <12> c15 i/o b3 <13> d15 i/o b3 <14> b14 i/o b3 <15> a14 i/o b3 <16> c14 i/o b3 <17> d14 i/o b3 <18> d13 i/o b3 <19> c13 i/o b3 <20> a13 i/o b3 <21> b13 i/o b3 <22> d12 i/o b3 <23> c12 i/o b4 <0> ae15 i/o b4 <1> af16 i/o b4 <2> ac16 i/o b4 <3> ad16 i/o b4 <4> ae16 i/o b4 <5> af17 i/o b4 <6> ae17 i/o b4 <7> ad17 i/o b4 <8> ac17 i/o b4 <9> af18 i/o b4 <10> ae18 i/o b4 <11> ad18 i/o b4 <12> b19 i/o b4 <13> a19 i/o b4 <14> d18 i/o b4 <15> c18 i/o b4 <16> b18 i/o b4 <17> a18 i/o b4 <18> d17 i/o b4 <19> c17 i/o b4 <20> b17 i/o b4 <21> a17 i/o b4 <22> b16 i/o b4 <23> c16 i/o b5 <0> ac18 i/o b5 <1> af19 i/o b5 <2> ae19 i/o b5 <3> aa19 i/o b5 <4> ad19 i/o b5 <5> ac19 i/o b5 <6> af20 i/o b5 <7> ae20 i/o b5 <8> ad20 i/o b5 <9> ac20 i/o b5 <10> af21 i/o b5 <11> ae21 i/o b5 <12> a22 i/o b5 <13> d21 i/o b5 <14> c21 i/o b5 <15> b21 i/o b5 <16> a21 i/o b5 <17> d20 i/o b5 <18> c20 i/o b5 <19> b20 i/o b5 <20> a20 i/o b5 <21> f19 i/o b5 <22> d19 i/o b5 <23> c19 i/o b6 <0> ad21 i/o b6 <1> ac21 i/o b6 <2> af22 i/o b6 <3> ae22 i/o b6 <4> ad22 i/o b6 <5> ac22 i/o b6 <6> af23 i/o b6 <7> ae23 i/o b6 <8> ad23 i/o b6 <9> af24 i/o b6 <10> ae24 i/o b6 <11> ad24 i/o b6 <12> a26 i/o b6 <13> d23 i/o b6 <14> b25 i/o b6 <15> a25 i/o b6 <16> b24 i/o b6 <17> a24 i/o b6 <18> c23 i/o b6 <19> b23 i/o b6 <20> a23 i/o b6 <21> d22 i/o b6 <22> c22 i/o b6 <23> b22
specifications isplsi 8840v 24 signal configuration isplsi 8840v 272-ball bga signal diagram 2019181716151413121110987654321 a a b b c c d vccio vccio vccio vccio vccio clk 1 clk 0 vccio vccio vccio vccio vccio clken vccio vccio vccio vccio vccio vccio vccio clk 2 epen vccio vccio ioclken vccio tck tdo gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd nc 1 gnd vcc vcc vcc vcc vcc vcc vcc toe set/ reset vcc tdi tms vcc vcc vcc vcc vcc vcc vcc vcc d e e f isplsi 8840v f g bottom view g h h j j k k l l m m n n p p r r t t u u v v w w y y 2019181716151413121110987654321 1. ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. i/o g5 <16> i/o g5 <23> i/o b6 <13> i/o b6 <17> i/o b6 <21> i/o b6 <22> i/o b4 <15> i/o b4 <16> i/o b4 <19> i/o b4 <22> i/o b0 <18> i/o b0 <21> i/o g5 <0> i/o g5 <3> i/o g5 <4> i/o g5 <5> i/o g5 <1> i/o g5 <2> i/o b0 <23> i/o g4 <6> i/o g4 <7> i/o g4 <5> i/o g4 <8> i/o g4 <1> i/o g4 <0> i/o g4 <3> i/o g3 <1> i/o g3 <0> i/o g4 <2> i/o g3 <4> i/o g3 <3> i/o g3 <2> i/o g3 <7> i/o g3 <6> i/o g3 <9> i/o g3 <8> i/o g3 <11> i/o g3 <10> i/o g3 <5> i/o g4 <4> i/o g2 <3> i/o g2 <2> i/o g2 <1> i/o g0 <11> i/o g2 <6> i/o g2 <5> i/o g2 <4> i/o g0 <10> i/o g2 <11> i/o g2 <8> i/o g2 <7> i/o g2 <9> i/o g2 <10> i/o b0 <20> i/o b0 <16> i/o b0 <15> i/o b0 <12> i/o b4 <21> i/o b4 <18> i/o b4 <17> i/o b4 <14> i/o b4 <12> i/o b6 <18> i/o b6 <12> i/o g5 <22> i/o g5 <19> i/o g5 <15> i/o g5 <14> i/o g5 <17> i/o g5 <20> i/o b6 <14> i/o b6 <16> i/o b6 <20> i/o b6 <23> i/o b4 <20> i/o b4 <23> i/o b0 <13> i/o b0 <17> i/o g5 <8> i/o g5 <9> i/o g5 <11> i/o g5 <10> i/o g5 <7> i/o g5 <6> i/o g4 <9> i/o g4 <10> i/o g4 <11> i/o b0 <22> i/o b0 <19> i/o b0 <14> i/o b4 <13> i/o b6 <19> i/o b6 <15> i/o g5 <18> i/o g5 <12> i/o g4 <12> i/o g4 <18> i/o g4 <14> i/o g5 <13> i/o g5 <21> i/o g4 <21> i/o g4 <19> i/o g4 <17> i/o g4 <13> i/o g2 <18> i/o g2 <19> i/o g2 <20> i/o g0 <13> i/o g2 <21> i/o g2 <22> i/o g2 <23> i/o g0 <12> i/o g0 <16> i/o b6 <9> i/o b6 <6> i/o b6 <2> i/o b4 <9> i/o b0 <10> i/o b0 <5> i/o b0 <4> i/o g0 <9> i/o g2 <0> i/o g0 <8> i/o g0 <7> i/o g0 <0> i/o b0 <1> i/o b0 <6> i/o b0 <2> i/o g0 <3> i/o g0 <5> i/o g0 <6> i/o g0 <4> i/o g0 <20> i/o g0 <19> i/o g0 <14> i/o g0 <15> i/o g0 <17> i/o b6 <8> i/o b6 <5> i/o b6 <1> i/o b4 <10> i/o b4 <7> i/o b4 <4> i/o b4 <0> i/o g0 <22> i/o b6 <10> i/o b6 <4> i/o b6 <0> i/o b4 <8> i/o b4 <6> i/o b4 <3> i/o b4 <1> i/o g0 <21> i/o g0 <23> i/o b6 <11> i/o b6 <7> i/o b6 <3> i/o b4 <11> i/o b4 <5> i/o b4 <2> i/o g0 <2> i/o g0 <1> i/o b0 <0> i/o b0 <3> i/o b0 <8> i/o b0 <9> i/o b0 <7> i/o b0 <11> i/o g0 <18> i/o g3 <20> i/o g3 <22> i/o g4 <22> i/o g3 <19> i/o g3 <21> i/o g3 <23> i/o g3 <16> i/o g3 <17> i/o g3 <18> i/o g3 <13> i/o g3 <14> i/o g3 <15> i/o g3 <12> i/o g2 <14> i/o g2 <13> i/o g2 <12> i/o g4 <20> i/o g2 <17> i/o g2 <15> i/o g2 <16> i/o g4 <23> i/o g4 <16> i/o g4 <15> nc 1 qioclk 1 qioclk 3 qioclk 0 nc 1 goe 1 goe 2 goe 0 goe 3 qioclk 2 272 bga/8840v.eps
specifications isplsi 8840v 25 signal configuration isplsi 8840 492-ball bga signal diagram 1. nc pins are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 i/o b6 <12> i/o b6 <15> i/o b6 <17> i/o b6 <20> i/o b5 <12> i/o b5 <16> i/o b5 <20> i/o b4 <13> i/o b4 <17> i/o b4 <21> i/o b3 <15> i/o b3 <20> i/o b2 <12> i/o b2 <15> i/o b2 <19> i/o b2 <23> i/o b1 <15> i/o b1 <19> i/o b1 <23> i/o b0 <16> i/o b0 <20> i/o b0 <23> i/o b0 <21> i/o b0 <22> i/o b0 <18> i/o b0 <14> i/o b1 <21> i/o b1 <17> i/o b1 <13> i/o b2 <21> i/o b2 <17> i/o b3 <23> i/o b3 <19> i/o b3 <16> i/o b3 <12> i/o b4 <23> i/o b4 <19> i/o b4 <15> i/o b5 <23> i/o b5 <18> i/o b5 <14> i/o b6 <22> i/o b6 <18> i/o b6 <13> i/o g5 <20> i/o g5 <16> i/o g4 <12> i/o g5 <13> i/o g5 <14> i/o g5 <15> i/o g4 <21> i/o g3 <20> i/o g4 <17> i/o g4 <22> i/o g4 <20> i/o g4 <19> i/o g4 <18> i/o g3 <23> i/o g4 <23> i/o g3 <22> i/o g3 <19> i/o g3 <14> i/o g2 <12> i/o g2 <13> i/o g3 <15> i/o g3 <13> i/o g3 <12> i/o g2 <14> i/o g2 <17> i/o g2 <16> i/o g2 <18> i/o g2 <23> i/o g1 <20> i/o g1 <15> i/o g0 <13> i/o g0 <17> i/o g0 <18> i/o g0 <19> i/o g0 <20> i/o g0 <14> i/o g0 <15> i/o g1 <14> i/o g1 <13> i/o g1 <12> i/o g1 <21> i/o g2 <20> i/o g1 <19> i/o g1 <18> i/o g1 <17> i/o g1 <16> i/o g0 <16> i/o g1 <23> i/o g1 <22> i/o g0 <12> i/o g2 <22> i/o g2 <21> i/o g2 <19> i/o g2 <15> i/o g3 <21> i/o g3 <18> i/o g3 <17> i/o g3 <16> i/o g5 <12> i/o g4 <15> i/o g4 <14> i/o g4 <13> i/o g4 <16> i/o g5 <17> i/o g5 <18> i/o g5 <19> i/o g5 <21> i/o g5 <22> i/o g5 <23> i/o b5 <21> i/o g5 <4> i/o g5 <8> i/o g5 <9> i/o g5 <10> i/o g5 <11> i/o g3 <3> i/o g4 <1> i/o g4 <7> i/o g4 <11> i/o g4 <0> i/o g3 <5> i/o g3 <4> i/o g3 <2> i/o g3 <6> i/o g3 <0> i/o g3 <1> i/o g4 <5> i/o g4 <4> i/o g4 <3> i/o g4 <2> i/o g4 <10> i/o g4 <9> i/o g4 <8> i/o g4 <6> i/o g5 <5> i/o g5 <6> i/o g5 <7> i/o b6 <21> i/o b5 <13> i/o b5 <17> i/o b5 <22> i/o b4 <14> i/o b4 <18> i/o b3 <13> i/o b3 <17> i/o b3 <18> i/o b3 <22> i/o b2 <16> i/o b2 <22> i/o b1 <14> i/o b1 <18> i/o b1 <22> i/o b0 <15> i/o b0 <19> i/o g5 <3> i/o g5 <2> i/o g5 <1> i/o g5 <0> i/o b0 <13> i/o b2 <13> i/o b0 <17> i/o b0 <12> i/o b1 <20> i/o b1 <16> i/o b1 <12> i/o b2 <20> i/o b2 <18> i/o b2 <14> i/o b3 <21> i/o b3 <14> i/o b4 <22> i/o b4 <20> i/o b4 <16> i/o b4 <12> i/o b5 <19> i/o b5 <15> i/o b6 <23> i/o b6 <19> i/o b6 <16> i/o b6 <14> clk2 epen qioclk 2 tck nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 goe 2 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd vccio vccio vccio vccio vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc nc 1 vcc nc 1 vcc vccio vccio vcc i/o g3 <10> i/o g3 <9> i/o g3 <7> i/o g3 <11> i/o g2 <11> i/o g2 <10> i/o g2 <9> i/o g2 <8> i/o g2 <4> i/o g2 <3> i/o g2 <5> i/o g2 <6> i/o g2 <0> i/o g1 <0> i/o g2 <1> i/o g1 <2> i/o g1 <3> i/o g1 <4> i/o g1 <5> i/o g1 <7> i/o g2 <2> i/o g1 <1> i/o g0 <8> i/o g0 <4> i/o b0 <10> i/o b2 <10> i/o g0 <23> i/o b6 <5> i/o b6 <1> i/o b5 <9> i/o b5 <5> i/o b5 <3> i/o b5 <0> i/o b4 <8> i/o b4 <2> i/o b3 <9> i/o b3 <8> i/o b3 <4> i/o b2 <11> i/o b2 <4> i/o b2 <0> i/o b1 <8> i/o b1 <4> i/o b1 <0> i/o b0 <7> i/o b0 <4> i/o b0 <8> i/o b1 <1> i/o b1 <5> i/o b1 <9> i/o b2 <1> i/o b2 <5> i/o b2 <9> i/o b3 <3> i/o b3 <7> i/o b3 <10> i/o b4 <3> i/o b4 <7> i/o b4 <11> i/o b5 <4> i/o b5 <8> i/o b6 <0> i/o b6 <4> i/o b6 <8> i/o b6 <11> i/o b6 <10> i/o b6 <7> i/o b6 <3> i/o b5 <11> i/o b5 <7> i/o b5 <2> i/o b4 <10> i/o b4 <6> i/o b4 <4> i/o b4 <0> i/o b3 <5> i/o b3 <1> i/o b2 <8> i/o b2 <6> i/o b2 <2> i/o b1 <10> i/o b1 <6> i/o b1 <2> i/o b1 <9> i/o b0 <5> i/o b0 <2> i/o b0 <0> i/o b0 <1> i/o b0 <3> i/o b0 <6> i/o b0 <11> i/o b1 <3> i/o b1 <7> i/o b1 <11> i/o b2 <3> i/o b2 <7> i/o b3 <0> i/o b3 <2> i/o b3 <6> i/o b3 <11> i/o b4 <1> i/o b4 <5> i/o b4 <9> i/o b5 <1> i/o b5 <6> i/o b5 <10> i/o b6 <2> i/o b6 <6> i/o b6 <9> i/o g0 <22> i/o g0 <21> i/o g0 <5> i/o g0 <6> i/o g0 <7> i/o g0 <3> i/o g0 <2> i/o g0 <1> i/o g0 <0> i/o g0 <9> i/o g0 <10> i/o g1 <11> i/o g1 <10> i/o g1 <9> i/o g1 <8> i/o g1 <6> i/o g0 <11> i/o g2 <7> i/o g3 <8> vcc vccio qioclk 3 goe 3 vcc vcc vcc vccio vccio set/ reset toe vccio vccio vcc gnd nc 1 gnd vccio vccio vcc vcc vcc vccio vccio goe 1 qioclk 1 vcc clk 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 ioclken nc 1 nc 1 vcc tdo nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 clk 0 qioclk 0 goe 0 tms nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 tdi gnd vccio vcc vcc vcc vcc vccio vccio vccio vccio vcc vcc vccio vcc nc 1 gnd nc 1 vccio vcc gnd gnd gnd clken vcc vcc vccio vccio vcc nc 1 gnd isplsi 8840v bottom view
specifications isplsi 8840v 26 device number grade blank = commercial isplsi 8840v - xxx x xxxx x speed 125 = 125 mhz f max 90 = 90 mhz f max 60 = 60 mhz f max power l = low package b272 = 272-ball bga (thermally enhanced) b492 = 492-ball bga device family 0212/8840v table 2-0041/8840v family f max (mhz) 125 ordering number package 492-ball bga t pd (ns) 8.5 isplsi isplsi 8840v-125lb492 125 272-ball bga 8.5 isplsi 8840v-125lb272 90 492-ball bga 10 isplsi 8840v-90lb492 90 272-ball bga 10 isplsi 8840v-90lb272 60 492-ball bga 15 isplsi 8840v-60lb492 60 272-ball bga 15 isplsi 8840v-60lb272 part number description ordering information commercial

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